HUAWEI Presents the Tau Scaling Law, Enabling Breakthroughs in Transistor Density and System Performance

On Monday, at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, He Tingbo, President of HUAWEI's Semiconductor Business Department, presented the Tau (τ) Scaling Law, ...
EDN

Taking power analysis to the transistor level for a full chip

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...
EDN

Synopsys Rolls Out Transistor-Level Static Timing Analysis

To address emerging custom circuit design challenges, Mountain View, Calif.-based EDA giant Synopsys Inc. today unveiled its anticipated next-generation transistor-level static timing analysis tool, ...
Semiconductor Engineering

Setting Vmin With Transistor-Level PDN Telemetry

Curious about how to precisely determine the optimal voltage-regulator setpoints for your System-on-Chip (SoC)? In this video, we dive into how transistor-level Power Delivery Network (PDN) telemetry ...
Tech Xplore on MSN

Low-power, flexible radio-frequency transistors break 100 GHz barrier

Over the past decades, electronics engineers worldwide have been trying to develop devices that could enable even faster ...
Electronic Design

GaN Transistors – Drive Control, Thermal Management, and Isolation

This year, several companies are expected to bring 600/650 V Gallium Nitride (GaN) power transistors to market. Almost all will be normally-on (depletion mode) transistors connected in a cascode ...