Seeking Alpha

Rambus: Short-Term Headwinds After A Year Of Super Growth

The diagram above by Rambus and Lumenci shows a Dual In-Line Memory Module (DIMM) which "is a module containing one or several Random Access Memory ('RAM') or Dynamic RAM ('DRAM') chips on a long, ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
Business Wire

Cypress' HyperBus™ Memory Interface for Instant-on Applications Incorporated into JEDEC xSPI Electrical Interface Standard

SAN JOSE, Calif.--(BUSINESS WIRE)--Cypress Semiconductor Corp. (Nasdaq: CY), a global leader in embedded systems solutions, today announced the inclusion of Cypress' high-bandwidth HyperBus™ 8-bit ...
EDN

Debugging DDR memory interfaces using area-based triggers

DDR bus protocol allows signals to go idle, or tri-state, when they are not active. When debugging or performing JEDEC conformance measurements on the DDR interface, it is often necessary to perform ...
Design-Reuse

Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions

Choosing the right type of memory is critical to ensure that the power and performance requirements are met for the target application. Memory technologies have significantly evolved over the last ...
Electronic Design

UMI Scales the Memory Wall in the Chiplet/Multi-Die Era

What are the current challenges involved with incorporating sufficient HBM into multi-die design? How a new interconnect technology can address the performance, size, and power issues that could ...
EDN

Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new ...