Microchip announced production qualification of its PolarFire MPFS250T SoC FPGA supporting the royalty-free RISC-V open standard ISA. Volume production of the MPFS250T, which provides 254,000 logic ...
The PolarFire SoC Discovery Kit from Microchip makes RISC-V and FPGA design accessible to a wider range of embedded engineers. This low-cost development platform allows students, beginners, and ...
A longtime supporter of the RISC-V (pronounced RISC Five) instruction set architecture (ISA), Microsemi provides tools and RISC-V soft cores for its various FPGA lines, including the recently unveiled ...
BERKELEY, Calif. & SANTA CLARA, Calif.--(BUSINESS WIRE)--Today at the RISC-V Summit, the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation ...
Microchip Technology has launched what it says is the industry’s first RISC-V based system-on-chip (SoC) field programmable gate array (FPGA) development kit, available for under $500. The rising ...
How a cool FPGA needs so little power. The importance of a smaller RISC-V SoC FPGA. What the PolarFire SoC means to RISC-V developers. Why security and reliability are key to PolarFire’s success. Very ...
Achronix has teamed up with Bluespec to offer a family of Linux-capable RISC-V soft processors for the Speedster7t FPGA family. “Bluespec’s RISC-V processors now integrate into the Achronix 2D network ...
With the PolarFire SoC Discovery Kit, Microchip makes RISC-V and FPGA hardware available to engineers working at all levels. The RISC-V architecture is never far from the news. However, away from the ...
Microchip’s PolarFire® SoC FPGA Icicle Kit enables the broad RISC-V-based Mi-V ecosystem for the industry’s lowest-power FPGA CHANDLER, Ariz., Sept. 16, 2020 (GLOBE NEWSWIRE) -- The rising adoption of ...
The BeagleV-Fire is a new single-board computer from BeagleBoard, the company behind the BeagleBone and BeaglePlay line of boards, among others. What makes this $150 board stand out is that it’s ...
A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao ...