A convergence of DFT techniques and the proliferation of in-silicon monitors can flag potential failures before they occur.

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Testing can represent as much as half the cost of semiconductor device manufacture. To reduce that, Mentor Graphics' TestKompress uses a new compression technology that lets designers cut the amount ...

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...