EDN

Reversing the SoC Design Process

It is obvious that IP-based system-on-chip (SoC) design or at least some form of “reuse methodology” is the way to address increasingly complex designs in shrinking time-to-market windows. But with ...
Semiconductor Engineering

Facilitating Complex SoC Design Through Automation And Integration

The boundaries between IP reuse, interconnect design, and hardware-software integration are no longer independent.
Nasdaq

Cadence Collaborates With Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm

Cadence 20.1 digital full flow tuned for Samsung Foundry advanced-process nodes, enabling optimal PPA and first-pass silicon success HPC reference flows based on iSpatial technology enable rapid ...
Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
EDN

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the ...
Design-Reuse

Synopsys and SMIC Team to Deliver Proven SoC Design Solution for 65-nm to 40-nm Process Nodes

MOUNTAIN VIEW, Calif. and SHANGHAI, Nov. 15, 2010 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and Semiconductor ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...
Embedded

How virtual prototypes aid SoC hardware design

The world of the hardware design engineer has changed dramatically in recent years. Designers no longer sit and code RTL in isolation to meet a paper specification, and then wait for a hardware ...
Embedded

Four key features every automotive SoC design needs

Vehicles can do much more than they were capable of a decade ago. Today’s modern connected vehicles have many convenient capabilities, from lane departure warnings to automated braking and ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial ...
TweakTown

Synopsys and Samsung achieve production tapeout of next-gen Exynos SoC on new 3nm process node

Synopsys and Samsung have announced its hit first production tapeout of its next-generation flagship mobile CPU on Samsung Foundry's GAA process. The companies announced that they have achieved ...
Business Wire

Cadence Collaborates With Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has optimized the Cadence ® digital 20.1 full flow for Samsung Foundry’s advanced-process ...