SANTA CLARA, Calif. — Japan's Advantest Corp. here has established a new U.S. R&D center that will help develop a future line of automatic test equipment (ATE) for system-on-a-chip (SoC) designs, ...

Pain points of the existing floorplan designing process. How artificial intelligence can optimize this process to reduce the time taken from weeks to just hours. Potential applications of expanding ...

At a time when artificial intelligence (AI)-centric system-on-chips (SoCs) are growing in size and complexity, network-on-chip (NoC) tiling hand in hand with mesh topology can support faster ...

Addressing challenges of using silicon IP, tracking IP cores, and taking advantage of the flexibility of modular design requires a proven process. It also requires a state-of-the-art IP management ...

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...