EDN

Self-timed interconnect solution supports AXI bus protocol

SAN FRANCISCO — EDA and intellectual property (IP) startup Silistix Ltd. has added support for the on-chip AMBA AXI bus protocol to the company's synthesized self-timed interconnect technology, ...
Semiconductor Engineering

Moving From AMBA ACE to CHI For Coherency

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in ...
Design-Reuse

UCIe Protocol Layer: AXI-S

The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Streaming AXI Bus and the FDI interface of the UCIe D2D Adapter. It allows for ...
Semiconductor Engineering

Min Lei

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in ...
EDN

Lower power, high-performance architecture for AMBA 3 AXI On-Chip Interconnect is unveiled

Winchester, UK – Synopsys, Inc., (Mountain View, California) software and IP specialists for semiconductor design and manufacturing, has enhanced its DesignWare IP for the ARM AMBA 3 AXI interconnect ...