Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal ...
EDN

Clock buffers pushing signal integrity boundaries

New clock fanout buffers claim to feature timing precision critical for high-speed infrastructure serving artificial intelligence (AI), cloud computing, and 5G/6G networks. These ultra-low jitter ...
EDN

Development of Technology that Achieves World’s Most Accurate On-Chip Measurement of Clock Signal Quality

NEC Corporation (NEC) and NEC Electronics Corporation (NEC Electronics) today announced the development and verification of technology that achieves the world's most accurate on-chip measurement of ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
Electronic Design

Real-Time Signal-Integrity Analysis on the 7 Series Oscilloscope

Tektronix’s 7 Series oscilloscope becomes a powerful signal-integrity tool where signal conditioning and integrity analysis can be easily performed on an advanced GUI. This demonstration by Misbah ...