RISC-V aims to break up the proprietary hold on processor design in exactly the same way that open-source software liberated huge swathes of the industry.

The RISC-V instruction set architecture is an open framework that allows design of a customized processor that can leverage tools and software libraries created for the standard versions.

RISC-V, an open source processor architecture that was created by academics, is gaining momentum in the market as a hardware alternative.

A recent catalyst for creating domain-specific processors has been the RISC-V ISA (Instruction Set Architecture). Since the usage of the ISA is open and royalty-free, it is an attractive basis on ...

The RISC-V Summit drew about 1,000 people to San Jose, California, this week to hear the latest on the open-source processor.

With Synopsys ARC-V Processor IP, customers will benefit from optimized and configurable implementations and the flexibility to leverage this extensive RISC-V ecosystem, which will help achieve their ...

In order to let AI automatically design a RISC-V CPU, the research team uses only external input/output observations instead of formal program code, and generates the CPU's logic circuit in a ...

How RISC-V verification ecosystems support flexibility in approaching a custom processor design.

There are several types of instruction set architectures that systematize the instructions that a processor can interpret and execute, typically x86 and ARM . RISC-V , which is one such ...

BeagleV is an affordable way to get your feet wet with RISC-V Linux computing. RISC-V is a CPU ISA (Instruction Set Architecture) family, like x86_64 (the architecture in most PCs and laptops) or ...

SiFive's RISC-V CPU cores will sit at the heart of NASA's future spaceflight processor.