IEEE

Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

Abstract: Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows.
CNX Software

AMD Kintex UltraScale+ Gen 2 mid-range FPGA family to be available until at least 2045

AMD Kintex UltraScale+ Gen 2 is a mid-range FPGA family designed for the broadcast, test, industrial, and medical markets, ...
GitHub

Python Parser and Creator of CBOE PITCH Messages

from pitch import AddOrderLong message = AddOrderLong.from_parms(time_offset=447_000, order_id='ORID0001', side='B', quantity=20_000, symbol='AAPL', price=0.9050 ...
elektormagazine

oHFM FPGA Module Standard Debuts as an Open, Vendor-Neutral Spec

oHFM FPGA Module Standard is now out as a free, open specification from SGET, aiming to reduce vendor lock-in and speed up FPGA/SoC-FPGA carrier design with a harmonized approach. The oHFM FPGA Module ...
IEEE

A Finite-Difference Time-Domain (FDTD) solver with linearly scalable performance in an FPGA cluster

Abstract: This paper presents an FPGA cluster-based Finite-Difference Time-Domain (FDTD) accelerator that offers a linear speedup with the number of FPGAs participating in computation within the ...